Add a pattern property for clock, also update the example with
a clock node
Signed-off-by: Rahul T R <r-ravikumar@xxxxxx>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index fa86691ebf16..e774a7f0bb08 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -48,6 +48,12 @@ patternProperties:
description:
This is the SERDES lane control mux.
+ "^clock@[0-9a-f]+$":
+ type: object
+ $ref: ../clock/ti,am654-ehrpwm-tbclk.yaml#
+ description:
+ This is TI syscon gate clk.
+
required:
- compatible
- reg
@@ -79,5 +85,11 @@ examples:
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
};
+
+ ehrpwm_tbclk: clock@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
};
...
--
2.17.1
