Il 23/05/22 12:47, Guillaume Ranquet ha scritto:
From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
This controller is present on several mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional difference,
so only one compatible field is added.
The controller can have two forms, as a normal display port and as an
embedded display port.
Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
---
.../display/mediatek/mediatek,dp.yaml | 99 +++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
new file mode 100644
index 000000000000..36ae0a6df299
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Port Controller
+
+maintainers:
+ - CK Hu <ck.hu@xxxxxxxxxxxx>
+ - Jitao shi <jitao.shi@xxxxxxxxxxxx>
+
+description: |
+ Device tree bindings for the MediaTek (embedded) Display Port controller
+ present on some MediaTek SoCs.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-dp-tx
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: faxi clock
+
+ clock-names:
+ items:
+ - const: faxi
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input endpoint of the controller, usually dp_intf
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the controller
+
You should add port@0 (and port@1, probably) as required... with what you've done
here, you're saying that "ports" is required, but you're allowing it to be empty..
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input endpoint of the controller, usually dp_intf
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the controller
required:
- port@0
- port@1
^^^ that's how it should look.
+ max-lanes:
+ maxItems: 1
+ description: maximum number of lanes supported by the hardware
+
+ max-linkrate:
+ maxItems: 1
+ description: maximum link rate supported by the hardware
As you've put it (in the example below), the max-linkrate property wants a value
that corresponds to what you find in the HW registers... this is wrong.
Devicetree bindings should be generic and devicetrees shouldn't have hardware
specific bits inside, hence, please change this property to accept a link rate
specified in Mbps and also specify that in the description.
Thanks,
Angelo
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ports
+ - max-lanes
+ - max-linkrate
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ edp_tx: edp_tx@1c500000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_pin>;
+ max-lanes = /bits/ 8 <4>;
+ max-linkrate = /bits/ 8 <0x1e>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
