Am Mittwoch, 18. Mai 2022, 02:25:29 CEST schrieb Rob Herring: > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Any value 0-2^32 is valid? funnily enough there really seems to be _no_ constraints defined in the spec [0] regarding the actual cache-block size. It essentially only states "The capacity and organization of a cache and the size of a cache block are both implementation-specific" and later in software-discovery: "The initial set of CMO extensions requires the following information to be discovered by software: - The size of the cache block for management and prefetch instructions - The size of the cache block for zero instructions" [0] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf > > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > What about hardware defined cache sizes? I'm scratching my head as to > what a 'software defined cache size' is. > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture >
