On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <atishp@xxxxxxxxxxxx> wrote:
>
> RISC-V ISA has sstc extension which allows updating the next clock event
> via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
> if sstc extension is available. Otherwise, it will fallback to SBI call
> to maintain backward compatibility.
>
> Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
> ---
> drivers/clocksource/timer-riscv.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 1767f8bf2013..d9398ae84a20 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -23,11 +23,24 @@
Add "#define pr_fmt(fmt)" here since you are using pr_info(...)
> #include <asm/sbi.h>
> #include <asm/timex.h>
>
> +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> +
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> + uint64_t next_tval = get_cycles64() + delta;
Use "u64" here to be consistent with other parts of the kernel.
> +
> csr_set(CSR_IE, IE_TIE);
> - sbi_set_timer(get_cycles64() + delta);
> + if (static_branch_likely(&riscv_sstc_available)) {
> +#if __riscv_xlen == 32
Use CONFIG_32BIT here.
> + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
> + csr_write(CSR_STIMECMPH, next_tval >> 32);
> +#else
> + csr_write(CSR_STIMECMP, next_tval);
> +#endif
> + } else
> + sbi_set_timer(next_tval);
> +
> return 0;
> }
>
> @@ -165,6 +178,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (error)
> pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
> error);
> +
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> + pr_info("Timer interrupt in S-mode is available via sstc extension\n");
> + static_branch_enable(&riscv_sstc_available);
> + }
> +
> return error;
> }
>
> --
> 2.25.1
>
Regards,
Anup
