Hi Krzysztof,
On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
> On 22/05/2022 17:50, Tomer Maimon wrote:
> > This adds initial device tree support for the
> > Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>
> Thank you for your patch. There is something to discuss/improve.
>
> > The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> > have various peripheral IPs.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@xxxxxxxxx>
> > + l2: l2-cache {
> > + compatible = "cache";
>
> Is this a real compatible? What bindings are you using here?
The compatible value and related properties are defined in the
Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
Shared Cache Nodes (/cpus/cpu*/l?-cache)").
The properties are handled by
dtschema/schemas/cache-controller.yaml, but the latter seems to lack
any checking on the compatible value?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
