Hi everyone, This series fixes the clock rate changing for the GPU. This work came about as part of adding DVFS support for the Mali GPU on MT8183, to support efforts in testing the SVS patches [1] on MT8183. This series fixes a couple things: 1. Fix the clock reference for the GPU. The device tree incorrectly references the top level PLL, when in fact it is fed from the clock gate in the MFGCFG block. Fixed in patch 1. 2. Clock rate requests on the MFG clock gate aren't propagated up the tree. Fixed in patch 2 by adding CLK_SET_RATE_PARENT. 3. MFG clock needs to be temporarily muxed away from MFG PLL during PLL reconfiguration, to avoid glitches. This is done using a notifier. The framework is added in patch 3, and added to the driver in patch 4. This is based on my "clk: mediatek: Move to struct clk_hw provider APIs" series version 3 [2], which was just merged. Please have a look. The GPU DVFS stuff will be sent separately, as that part is a bit more contentious, and the changes span more subsystems. Regards ChenYu [1] https://lore.kernel.org/linux-mediatek/20220516004311.18358-1-roger.lu@xxxxxxxxxxxx/ [2] https://lore.kernel.org/linux-mediatek/20220519071610.423372-1-wenst@xxxxxxxxxxxx/ Chen-Yu Tsai (4): arm64: dts: mt8183: Fix Mali GPU clock clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: Add clk mux notifier for MFG mux arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 ++-- drivers/clk/mediatek/clk-mt8183.c | 21 ++++++++++++ drivers/clk/mediatek/clk-mux.c | 42 ++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 15 +++++++++ 5 files changed, 82 insertions(+), 4 deletions(-) -- 2.36.1.124.g0e6072fb45-goog
