On Fri, May 13, 2022 at 08:26:20PM +0300, Dmitry Baryshkov wrote:
> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Thus, to receive higher MSI vectors properly,
> declare that the host should use split MSI IRQ handling on these
> platforms.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 2e5464edc36e..f79752d1d680 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -194,6 +194,7 @@ struct qcom_pcie_ops {
>
> struct qcom_pcie_cfg {
> const struct qcom_pcie_ops *ops;
> + unsigned int has_split_msi_irq:1;
> unsigned int pipe_clk_need_muxing:1;
> unsigned int has_tbu_clk:1;
> unsigned int has_ddrss_sf_tbu_clk:1;
> @@ -1502,6 +1503,7 @@ static const struct qcom_pcie_cfg ipq8064_cfg = {
>
> static const struct qcom_pcie_cfg msm8996_cfg = {
> .ops = &ops_2_3_2,
> + .has_split_msi_irq = true,
> };
> @@ -1592,6 +1599,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>
> pcie->cfg = pcie_cfg;
>
> + if (pcie->cfg->has_split_msi_irq) {
> + pp->num_vectors = MAX_MSI_IRQS;
> + pp->has_split_msi_irq = true;
> + }
> +
> pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> if (IS_ERR(pcie->reset)) {
> ret = PTR_ERR(pcie->reset);
So if you fix dwc core to always infer num_vectors when passed in as 0
as I just suggested, then this patch isn't needed.
It also avoids having to pass in MAX_MSI_IRQS (or complicate the qcom
driver) for sc8280xp which only uses four "msi" GIC interrupts and hence
only MAX_MSI_IRQS/2 vectors.
Johan
