+David Kruckemyer (who is chairing the CMO task-group within RVI). On Wed, 18 May 2022 at 02:25, Rob Herring <robh@xxxxxxxxxx> wrote: > > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Any value 0-2^32 is valid? > > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > What about hardware defined cache sizes? I'm scratching my head as to > what a 'software defined cache size' is. This seems to be a misnomer, as the specification doesn't use the term and rather talks about the "size of a cache block for [operation name]". There are currently two such 'operation sizes' discoverable by software: - size of the cache block for management and prefetch instructions - size of the cache block for zero instructions For whatever it's worth, cache operations in RISC-V attempt to disassociate the underlying hardware cache geometry from software. See https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf for the CMO specification, and the discoverable parameters are listed in section 2.7. Philipp. > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > > -- > > 2.35.1 > > > >
