On Tue, 17 May 2022 15:35:17 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@xxxxxxx> > > i.MX MU has a MUR bit which is to reset both the Processor B and the > Processor A sides of the MU module, forcing all control and status > registers to return to their default values (except the BHR bit in the ACR > register and BHRM bit in BCR register), and all internal states to be > cleared. > > Signed-off-by: Peng Fan <peng.fan@xxxxxxx> > --- > Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
