On Mon, May 09, 2022 at 07:31:31PM -0700, Guenter Roeck wrote: > On 5/8/22 12:43, Jonathan Neuschäfer wrote: > > On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral > > clocks are individually gated and ungated. Therefore, the watchdog > > driver must be able to ungate the watchdog clock. > > > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> > > --- > > > > v3: > > - Add enable/disable calls to npcm_wdt_restart handler > > - Not applied due to the above change: Acked-by: Guenter Roeck <linux@xxxxxxxxxxxx> > > > > v2: > > - https://lore.kernel.org/lkml/20220429172030.398011-4-j.neuschaefer@xxxxxxx/ > > - Add clk_disable_unprepare call, suggested by Guenter Roeck > > > > v1: > > - https://lore.kernel.org/lkml/20220422183012.444674-4-j.neuschaefer@xxxxxxx/ > > --- [...] > > @@ -147,9 +155,15 @@ static int npcm_wdt_restart(struct watchdog_device *wdd, > > { > > struct npcm_wdt *wdt = to_npcm_wdt(wdd); > > > > + if (wdt->clk) > > + clk_prepare_enable(wdt->clk); > > + > > writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); > > udelay(1000); > > > > + if (wdt->clk) > > + clk_disable_unprepare(wdt->clk); > > + > > I am trying to understand why you stop the clock here. > If the watchdog didn't reset the system by now, for whatever reason, > you explicitly don't want it to reset the system ? If so, please add > a comment describing the reason for stopping the clock here. It was for symmetry with starting the clock, and in the hope that udelay(1000) will be enough to reach timer expiration. (In practice it does appear to work, although 1ms is not much.) Upon reconsideration, I agree it's better to leave the clock running for reset (with a comment pointing out the asymmetry). Best regards, Jonathan
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