Hello Rob and Marc, thanks for comment and help. This patch is marked as RFC and not intended for direct application. We plan to gather feetback, adjust code and probably even IP core HDL based on suggestions, then we plan more testing and when we will be ready and time allows, new version with plea for merge will provided. On Monday 16 of May 2022 18:34:45 Marc Kleine-Budde wrote: > On 16.05.2022 11:02:50, Rob Herring wrote: > > On Fri, May 13, 2022 at 01:27:06AM +0200, Matej Vasilevski wrote: > > > Extend dt-bindings for CTU CAN-FD IP core with necessary properties > > > to enable HW timestamping for platform devices. Since the timestamping > > > counter is provided by the system integrator usign those IP cores in > > > their FPGA design, we need to have the properties specified in device > > > tree. > > > > > > Signed-off-by: Matej Vasilevski <matej.vasilevski@xxxxxxxxx> > > > --- > > > .../bindings/net/can/ctu,ctucanfd.yaml | 34 +++++++++++++++++-- > > > 1 file changed, 31 insertions(+), 3 deletions(-) > > > > What's the base for this patch? Doesn't apply for me. It is based on the series of complete CTU CAN FD support which has been accepted into net-next. The DTC part has gone through your review and has been ACKed longer time ago. We have spent considerable time to resolve suggested driver changes - headers files generation from HDL tool chain, etc. We inline to version when most of the info will be directly provided by the core HW except for optional second clocks probably. Best wishes, Pavel > > > diff --git > > > a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > > > b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml index > > > fb34d971dcb3..c3693dadbcd8 100644 > > > --- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > > > +++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > > > @@ -41,9 +41,35 @@ properties: > > > > > > clocks: > > > description: | > > > - phandle of reference clock (100 MHz is appropriate > > > - for FPGA implementation on Zynq-7000 system). > > > + Phandle of reference clock (100 MHz is appropriate for FPGA > > > + implementation on Zynq-7000 system). If you wish to use > > > timestamps + from the core, add a second phandle with the clock > > > used for timestamping + (can be the same as the first clock). > > > + maxItems: 2 > > > > With more than 1, you have to define what each entry is. IOW, use > > 'items'. > > > > > + > > > + clock-names: > > > + description: | > > > + Specify clock names for the "clocks" property. The first clock > > > name + doesn't matter, the second has to be "ts_clk". Timestamping > > > frequency + is then obtained from the "ts_clk" clock. This takes > > > precedence over + the ts-frequency property. > > > + You can omit this property if you don't need timestamps. > > > + maxItems: 2 > > > > You must define what the names are as a schema. > > > > > + > > > + ts-used-bits: > > > + description: width of the timestamping counter > > > + maxItems: 1 > > > + items: > > > > Not an array, so you don't need maxItems nor items. > > > > > + minimum: 8 > > > + maximum: 64 > > > + > > > + ts-frequency: > > > > Use a standard unit suffix. > > > > > + description: | > > > + Frequency of the timestamping counter. Set this if you want to > > > get + timestamps, but you didn't set the timestamping clock in > > > clocks property. maxItems: 1 > > > + items: > > > > Not an array. > > > > > > Is timestamping a common feature for CAN or is this specific to this > > controller? In the latter case, you need vendor prefixes on these > > properties. In the former case, you need to define them in a common > > schema. > > This property describes the usable with of the free running timer and > the timestamps generated by it. This is similar to the free running > timer and time stamps as found on PTP capable Ethernet NICs. But the > ctucanfd comes in a hardware description language that can be > parametrized and synthesized into your own FPGA. > > To answer your question, timestamping is common in newer CAN cores, but > the width of the timestamping register is usually fixed and thus hard > coded in the driver. > > regards, > Marc
