On 13/05/2022 15:39, Dmitry Baryshkov wrote:
On 13/05/2022 11:58, Johan Hovold wrote:
On Thu, May 12, 2022 at 01:45:35PM +0300, Dmitry Baryshkov wrote:
I have replied with my Tested-by to the patch at [2], which has landed
in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom:
Add support for handling MSIs from 8 endpoints"). However lately I
noticed that during the tests I still had 'pcie_pme=nomsi', so the
device was not forced to use higher MSI vectors.
After removing this option I noticed that hight MSI vectors are not
delivered on tested platforms. After additional research I stumbled upon
a patch in msm-4.14 ([1]), which describes that each group of MSI
vectors is mapped to the separate interrupt. Implement corresponding
mapping.
The first patch in the series is a revert of [2] (landed in pci-next).
Either both patches should be applied or both should be dropped.
Patchseries dependecies: [3] (for the schema change).
Changes since v7:
- Move code back to the dwc core driver (as required by Rob),
- Change dt schema to require either a single "msi" interrupt or an
array of "msi0", "msi1", ... "msi7" IRQs. Disallow specifying a
part of the array (the DT should specify the exact amount of MSI
IRQs
allowing fallback to a single "msi" IRQ),
Why this new constraint?
I've been using your v7 with an sc8280xp which only has four IRQs (and
hence 128 MSIs).
Looks like this version of the series would not allow that anymore.
As a second thought, let's relax parsing needs.
Hmm, with num_vectors being specified in the qcom cfg data, this is not
required anymore.
--
With best wishes
Dmitry
