On Fri, 13 May 2022 at 14:55, Johan Hovold <johan@xxxxxxxxxx> wrote:
>
> On Thu, May 12, 2022 at 01:45:45PM +0300, Dmitry Baryshkov wrote:
> > On SM8250 each group of MSI interrupts is mapped to the separate host
> > interrupt. Describe each of interrupts in the device tree for PCIe0
> > host.
> >
> > Tested on Qualcomm RB5 platform with first group of MSI interrupts being
> > used by the PME and attached ath11k WiFi chip using second group of MSI
> > interrupts.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index 410272a1e19b..ef683a2f7412 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 {
> > ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> > <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> >
> > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7";
>
> You must use "msi0" instead of "msi" or you only get 32 MSI regardless
> of what follows currently (and this wouldn't pass DT validation either).
Yes. And that's why I didn't notice that I broke msi0 parsing.
>
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 0x7>;
> > interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>
> Johan
--
With best wishes
Dmitry
