Only if you have other occasion to repost, in subject:
PCI: dwc: Split
On Thu, May 12, 2022 at 01:45:40PM +0300, Dmitry Baryshkov wrote:
> Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init()
> function. The code is complex enough to warrant a separte function.
s/separte/separate/
It looks like this is simply a split, with no expected functional
impact. The above is sufficient; the sentence below is not really
necessary.
> Adding another bit to support multiple host MSI IRQs would make it
> overcomplicated.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> .../pci/controller/dwc/pcie-designware-host.c | 97 +++++++++++--------
> 1 file changed, 55 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 5f6590929319..6b0c7b75391f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -288,6 +288,59 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
> }
>
> +static int dw_pcie_msi_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct platform_device *pdev = to_platform_device(pci->dev);
> + int ret;
> + u32 ctrl, num_ctrls;
> +
> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> + pp->irq_mask[ctrl] = ~0;
> +
> + if (!pp->msi_irq[0]) {
> + int irq = platform_get_irq_byname_optional(pdev, "msi");
> +
> + if (irq < 0) {
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> + }
> + pp->msi_irq[0] = irq;
> + }
> +
> + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> +
> + ret = dw_pcie_allocate_domains(pp);
> + if (ret)
> + return ret;
> +
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> + dw_chained_msi_isr,
> + pp);
> +
> + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> + if (ret)
> + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> +
> + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
> + sizeof(pp->msi_msg),
> + DMA_FROM_DEVICE,
> + DMA_ATTR_SKIP_CPU_SYNC);
> + ret = dma_mapping_error(pci->dev, pp->msi_data);
> + if (ret) {
> + dev_err(pci->dev, "Failed to map MSI data: %d\n", ret);
> + pp->msi_data = 0;
> + dw_pcie_free_msi(pp);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> int dw_pcie_host_init(struct pcie_port *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -365,49 +418,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (ret < 0)
> return ret;
> } else if (pp->has_msi_ctrl) {
> - u32 ctrl, num_ctrls;
> -
> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> - for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> - pp->irq_mask[ctrl] = ~0;
> -
> - if (!pp->msi_irq[0]) {
> - int irq = platform_get_irq_byname_optional(pdev, "msi");
> -
> - if (irq < 0) {
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0)
> - return irq;
> - }
> - pp->msi_irq[0] = irq;
> - }
> -
> - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> -
> - ret = dw_pcie_allocate_domains(pp);
> - if (ret)
> + ret = dw_pcie_msi_host_init(pp);
> + if (ret < 0)
> return ret;
> -
> - for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> - if (pp->msi_irq[ctrl] > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> - dw_chained_msi_isr,
> - pp);
> -
> - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> - if (ret)
> - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> -
> - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
> - sizeof(pp->msi_msg),
> - DMA_FROM_DEVICE,
> - DMA_ATTR_SKIP_CPU_SYNC);
> - ret = dma_mapping_error(pci->dev, pp->msi_data);
> - if (ret) {
> - dev_err(pci->dev, "Failed to map MSI data: %d\n", ret);
> - pp->msi_data = 0;
> - goto err_free_msi;
> - }
> }
> }
>
> --
> 2.35.1
>
