Document the Ethernet AVB IP found on RZ/V2M SoC.
It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
access controller (DMAC) for transferring transmitted Ethernet frames
to and received Ethernet frames from respective storage areas in the
RAM at high speed.
The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
synchronization protocol, IEEE 802.1Qav real-time transfer, and the
IEEE 802.1Qat stream reservation protocol.
R-Car has a pair of combined interrupt lines:
ch22 = Line0_DiA | Line1_A | Line2_A
ch23 = Line0_DiB | Line1_B | Line2_B
Line0 for descriptor interrupts (which we call dia and dib).
Line1 for error related interrupts (which we call err_a and err_b).
Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
RZ/V2M hardware has separate interrupt lines for each of these.
It has 3 clocks; the main AXI clock, the AMBA CHI (Coherent Hub
Interface) clock and a gPTP reference clock.
Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v3:
- No change
v2:
- Instead of reusing ch22 and ch24 interupt names, use the proper names
---
.../bindings/net/renesas,etheravb.yaml | 82 ++++++++++++++-----
1 file changed, 61 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index ee2ccacc39ff..acf347f3cdbe 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -43,6 +43,11 @@ properties:
- renesas,etheravb-r8a779a0 # R-Car V3U
- const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
+ - items:
+ - enum:
+ - renesas,etheravb-r9a09g011 # RZ/V2M
+ - const: renesas,etheravb-rzv2m # RZ/V2M compatible
+
- items:
- enum:
- renesas,r9a07g043-gbeth # RZ/G2UL
@@ -160,16 +165,33 @@ allOf:
- const: arp_ns
rx-internal-delay-ps: false
else:
- properties:
- interrupts:
- minItems: 25
- maxItems: 25
- interrupt-names:
- items:
- pattern: '^ch[0-9]+$'
- required:
- - interrupt-names
- - rx-internal-delay-ps
+ if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,etheravb-rzv2m
+ then:
+ properties:
+ interrupts:
+ minItems: 29
+ maxItems: 29
+ interrupt-names:
+ items:
+ pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
+ rx-internal-delay-ps: false
+ required:
+ - interrupt-names
+ else:
+ properties:
+ interrupts:
+ minItems: 25
+ maxItems: 25
+ interrupt-names:
+ items:
+ pattern: '^ch[0-9]+$'
+ required:
+ - interrupt-names
+ - rx-internal-delay-ps
- if:
properties:
@@ -231,17 +253,35 @@ allOf:
- const: chi
- const: refclk
else:
- properties:
- clocks:
- minItems: 1
- items:
- - description: AVB functional clock
- - description: Optional TXC reference clock
- clock-names:
- minItems: 1
- items:
- - const: fck
- - const: refclk
+ if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,etheravb-rzv2m
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+ - description: Coherent Hub Interface clock
+ - description: gPTP reference clock
+ clock-names:
+ items:
+ - const: axi
+ - const: chi
+ - const: gptp
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ items:
+ - description: AVB functional clock
+ - description: Optional TXC reference clock
+ clock-names:
+ minItems: 1
+ items:
+ - const: fck
+ - const: refclk
additionalProperties: false
--
2.32.0
