Quoting Sankeerth Billakanti (QUIC) (2022-05-05 11:47:20) > >Quoting Sankeerth Billakanti (2022-05-05 11:02:36) > >> > >> Our internal power grid documents list the regulators as VDD_A_*_1P2 > >> and VDD_A_*_0P9 for all the platforms. > > > >Do your internal power grid documents indicate what these supplies are > >powering? The question is if these supplies power any of the logic inside the > >eDP controller or if they only supply power to the analog circuits in the eDP > >phy. If it's the eDP phy only then the regulator usage in the eDP driver should > >be removed. I would suspect this is the case because the controller is > >probably all digital logic and runs at the typical 1.8V that the rest of the SoC > >uses. Similarly, these are voltage references which sound like a PLL reference > >voltage. > > > >Please clarify this further. > > > > For the DP driver using the usb-dp combo phy, there were cases where the usb driver > was turning off the phy and pll regulators whenever usb-dp concurrent mode need not be supported. > This caused phy and pll to be powered down causing aux transaction failures and display blankouts. > From then on, it became a practice for the controller driver to vote for the phy and pll regulators also. > That sounds like USB-DP combo phy driver had improper regulator power management where aux transactions from DP didn't keep the power on to the phy. Where does the power physically go? If the power isn't physically going to the DP controller it shouldn't be controlled from the DP controller driver. If the aux bus needs the DP phy enabled, the DP controller driver should enable the phy power (via phy_power_on()?).
