On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote:
> From: Xinlei Lee <xinlei.lee@xxxxxxxxxxxx>
>
> Convert mediatek,dsi.txt to mediatek,dsi.yaml format
>
> Signed-off-by: Xinlei Lee <xinlei.lee@xxxxxxxxxxxx>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx>
> ---
> .../display/mediatek/mediatek,dsi.txt | 62 ---------
> .../display/mediatek/mediatek,dsi.yaml | 122 ++++++++++++++++++
> 2 files changed, 122 insertions(+), 62 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> deleted file mode 100644
> index 36b01458f45c..000000000000
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -Mediatek DSI Device
> -===================
> -
> -The Mediatek DSI function block is a sink of the display subsystem and can
> -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
> -channel output.
> -
> -Required properties:
> -- compatible: "mediatek,<chip>-dsi"
> -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> -- reg: Physical base address and length of the controller's registers
> -- interrupts: The interrupt signal from the function block.
> -- clocks: device clocks
> - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> -- clock-names: must contain "engine", "digital", and "hs"
> -- phys: phandle link to the MIPI D-PHY controller.
> -- phy-names: must contain "dphy"
> -- port: Output port node with endpoint definitions as described in
> - Documentation/devicetree/bindings/graph.txt. This port should be connected
> - to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
> -
> -Optional properties:
> -- resets: list of phandle + reset specifier pair, as described in [1].
> -
> -[1] Documentation/devicetree/bindings/reset/reset.txt
> -
> -MIPI TX Configuration Module
> -============================
> -
> -See phy/mediatek,dsi-phy.yaml
> -
> -Example:
> -
> -mipi_tx0: mipi-dphy@10215000 {
> - compatible = "mediatek,mt8173-mipi-tx";
> - reg = <0 0x10215000 0 0x1000>;
> - clocks = <&clk26m>;
> - clock-output-names = "mipi_tx0_pll";
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - drive-strength-microamp = <4600>;
> - nvmem-cells= <&mipi_tx_calibration>;
> - nvmem-cell-names = "calibration-data";
> -};
> -
> -dsi0: dsi@1401b000 {
> - compatible = "mediatek,mt8173-dsi";
> - reg = <0 0x1401b000 0 0x1000>;
> - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
> - <&mipi_tx0>;
> - clock-names = "engine", "digital", "hs";
> - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
> - phys = <&mipi_tx0>;
> - phy-names = "dphy";
> -
> - port {
> - dsi0_out: endpoint {
> - remote-endpoint = <&panel_in>;
> - };
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> new file mode 100644
> index 000000000000..2ca9229ef69e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> @@ -0,0 +1,122 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek DSI Controller Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx>
> + - Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> + - Jitao Shi <jitao.shi@xxxxxxxxxxxx>
> + - Xinlei Lee <xinlei.lee@xxxxxxxxxxxx>
> +
> +description: |
> + The MediaTek DSI function block is a sink of the display subsystem and can
> + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
> + channel output.
> +
> +allOf:
> + - $ref: /schemas/display/dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt2701-dsi
> + - mediatek,mt7623-dsi
> + - mediatek,mt8167-dsi
> + - mediatek,mt8173-dsi
> + - mediatek,mt8183-dsi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Engine Clock
> + - description: Digital Clock
> + - description: HS Clock
> +
> + clock-names:
> + items:
> + - const: engine
> + - const: digital
> + - const: hs
> +
> + resets:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port node. This port should be connected to the input
> + port of an attached DSI panel or DSI-to-eDP encoder chip.
> +
> +
1 blank line
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
Did you try adding these? Because they are wrong and will contradict
dsi-controller.yaml.
Rob
