sv57 is defined in the RISC-V Privileged Specification document.
Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.
Add riscv,sv57 to the list of valid mmu-type values.
Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
+ - riscv,sv57
- riscv,none
riscv,isa:
--
2.35.1
