Am Sonntag, 1. Mai 2022, 13:48:02 CEST schrieb Peter Geis:
> On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@xxxxxxxxx> wrote:
> >
> > Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> > >
> > > On 4/29/22 13:52, Peter Geis wrote:
> > > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > > This board ouputs debug on uart2 and supports the following components:
> > > > Gigabit Ethernet
> > > > USB2 x2 (one port otg capable)
> > > > USB3
> > > > PCIe/SATA M2
> > > > HDMI
> > > > DSI (RPi compatible pinout)
> > > > CSI (RPi compatible pinout)
> > > > A/B/G/N WiFi
> > > > Bluetooth
> > > > SDMMC
> > > > eMMC
> > > > SPI Flash
> > > > PI-40 compatible pin header
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
> > > > ---
> > > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > > 2 files changed, 616 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > new file mode 100644
> > > > index 000000000000..184ab7e1d178
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > @@ -0,0 +1,615 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + *
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > > +#include "rk3566.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > > +
> > >
> > > [..]
> > >
> > > > +
> > > > +&mdio1 {
> > >
> > > > + rgmii_phy1: ethernet-phy@0 {
> > > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > > + reg = <0x1>;
> > >
> > > Hi,
> > >
> > > The reg value doesn't match the node name.
> > > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > > Could you check?
> >
> > I do have an older Quartz-B in my boardfarm and in that older
> > devicetree the phy-reg also is "0" instead of the "1" used here.
> >
> > Is that a hardware-change?
>
> The ethernet maintainers previously brought up that 0x0 is the
> broadcast address for the mdio-bus. They requested we put the actual
> bus id of the phy even on single phy busses. This is the first one
> I've confirmed the bus address on.
>
> Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
> mentioned this. Strange dtbs-check doesn't catch this, would you fix
> it in line Heiko
no that's ok, I can fix that up. Just wanted to clarify what the intention
was first :-)
> or do you want another revision?
>
> >
> > Thanks
> > Heiko
> >
> >
>
