On 29/04/2022 19:20, Jonathan Neuschäfer wrote: > The Nuvoton WPCM450 SoC has a combined clock and reset controller. > Add a devicetree binding for it, as well as definitions for the bit > numbers used by it. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> > --- > > v2: > - Various improvements, suggested by Krzysztof Kozlowski > > v1: > - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@xxxxxxx/ > --- > .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ > .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ > 2 files changed, 133 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > new file mode 100644 > index 0000000000000..3ed3e40e39637 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton WPCM450 clock controller > + > +maintainers: > + - Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> > + > +description: > + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to > + the rest of the chip. > + > +properties: > + compatible: > + const: nuvoton,wpcm450-clk > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Reference clock oscillator (should be 48 MHz) > + > + clock-names: > + items: > + - const: refclk Sorry for not bringing it up earlier - this should be just "ref". Names in values should not have suffixes (so no "tx-dma", "wake-gpio", "ref-clk" etc). Best regards, Krzysztof
