Add GPT support by adding pwm nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 192 +++++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 4f9a84d7af08..e5cbe941aead 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -168,6 +168,198 @@ soc: soc {
#size-cells = <2>;
ranges;
+ gpt0: pwm@10048000 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048000 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@10048100 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048100 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt2: pwm@10048200 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048200 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt3: pwm@10048300 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048300 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt4: pwm@10048400 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048400 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt5: pwm@10048500 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048500 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt6: pwm@10048600 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048600 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt7: pwm@10048700 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048700 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g044-ssi",
"renesas,rz-ssi";
--
2.25.1
