On 28/04/2022 13:56, Rex-BC Chen wrote: > To support reset of infra_ao, add the bit definitions for MT8192. > There are 5 banks for infra reset and 32 bits for each bank. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx> > --- > include/dt-bindings/reset/mt8192-resets.h | 163 ++++++++++++++++++++++ > 1 file changed, 163 insertions(+) > > diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h > index be9a7ca245b9..5863d138568a 100644 > --- a/include/dt-bindings/reset/mt8192-resets.h > +++ b/include/dt-bindings/reset/mt8192-resets.h > @@ -7,6 +7,7 @@ > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 > #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 > > +/* TOPRGU resets */ > #define MT8192_TOPRGU_MM_SW_RST 1 > #define MT8192_TOPRGU_MFG_SW_RST 2 > #define MT8192_TOPRGU_VENC_SW_RST 3 > @@ -27,4 +28,166 @@ > > #define MT8192_TOPRGU_SW_RST_NUM 23 > > +/* INFRA RST0 */ > +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 > +#define MT8192_INFRA_RST0_USB_TOP_SWRST 1 > +#define MT8192_INFRA_RST0_AP_MD_CCIF_4_SWRST 2 > +#define MT8192_INFRA_RST0_MM_IOMMU_SWRST 3 > +#define MT8192_INFRA_RST0_MSDC3_SWRST 4 > +#define MT8192_INFRA_RST0_MSDC2_SWRST 5 > +#define MT8192_INFRA_RST0_MSDC1_SWRST 6 > +#define MT8192_INFRA_RST0_MSDC0_SWRST 7 > +#define MT8192_INFRA_RST0_AP_DMA_SWRST 8 > +#define MT8192_INFRA_RST0_MIPI_D_SWRST 9 > +#define MT8192_INFRA_RST0_MIPI_C_SWRST 10 > +#define MT8192_INFRA_RST0_BTIF_SWRST 11 > +#define MT8192_INFRA_RST0_SSUSB_TOP_SWRST 12 > +#define MT8192_INFRA_RST0_DISP_PWM_SWRST 13 > +#define MT8192_INFRA_RST0_AUXADC_SWRST 14 > +#define MT8192_INFRA_RST0_RSV0 15 > +#define MT8192_INFRA_RST0_RSV1 16 > +#define MT8192_INFRA_RST0_RSV2 17 > +#define MT8192_INFRA_RST0_RSV3 18 > +#define MT8192_INFRA_RST0_RSV4 19 > +#define MT8192_INFRA_RST0_RSV5 20 > +#define MT8192_INFRA_RST0_RSV6 21 > +#define MT8192_INFRA_RST0_RSV7 22 > +#define MT8192_INFRA_RST0_RSV8 23 > +#define MT8192_INFRA_RST0_RSV9 24 > +#define MT8192_INFRA_RST0_RSV10 25 > +#define MT8192_INFRA_RST0_RSV11 26 > +#define MT8192_INFRA_RST0_RSV12 27 > +#define MT8192_INFRA_RST0_RSV13 28 > +#define MT8192_INFRA_RST0_RSV14 29 > +#define MT8192_INFRA_RST0_RSV15 30 > +#define MT8192_INFRA_RST0_RSV16 31 Same problem as with previous patch - these are not IDs, but register values with gaps. Best regards, Krzysztof
