Il 28/04/22 08:17, Allen-KH Cheng ha scritto:
Add basic chip support for MediaTek MT8186. Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@xxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 232 +++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 949 ++++++++++++++++++++ 3 files changed, 1182 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c7d4636a2cb7..50a2c58c5f56 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000000..6bf5b81e3e6b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,232 @@
..snip..
+ +&pio { + i2c0_pins: i2c0{ + pins_bus {
No underscores please! Either name this "pins-bus" or, more appropriately, I would give it a more descriptive name, like "pins-sda-scl".
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>, + <PINMUX_GPIO127__FUNC_SCL0>; + bias-disable; + mediatek,drive-strength-adv =<0>; + drive-strength = <MTK_DRIVE_4mA>; + input-enable; + }; + };
..snip..
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi new file mode 100644 index 000000000000..9e3d45f3e5de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng <allenn-kh.cheng@xxxxxxxxxxxx>
Uhm, you typoed your email address! :-)
+ */ +/dts-v1/; +#include <dt-bindings/clock/mt8186-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mt8186-pinfunc.h> +#include <dt-bindings/power/mt8186-power.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/mt8186-resets.h> + +/ { + compatible = "mediatek,mt8186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>;
No capacity-dmips-mhz for the CPUs?!
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + };
..snip..
+ soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Are there no ppi-partitions for this interrupt controller?
+ }; +
..snip..
+ + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8186-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: mfg0@MT8186_POWER_DOMAIN_MFG0 {
This should be, for consistency with other mtk devicetrees: mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
+ reg = <MT8186_POWER_DOMAIN_MFG0>; + clocks = <&topckgen CLK_TOP_MFG>; + clock-names= "mfg00"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + mfg1@MT8186_POWER_DOMAIN_MFG1 {
power-domain@MT8186_POWER_DOMAIN_MFG1 ....and the same for all of the other occurrences.
+ reg = <MT8186_POWER_DOMAIN_MFG1>; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>;
..snip..
+ + scp: scp@10500000 { + compatible = "mediatek,mt8186-scp"; + reg = <0 0x10500000 0 0x40000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + status = "okay";
`status = "okay"` can be omitted here: all the nodes are enabled by default.
+ }; +
Cheers, Angelo