On 26/04/2022 15:21, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx> > > Add compatibles for PCIe v3 General Register Files. > > Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx> > > --- > changes in v2: > - add soc-part to pcie3-phy-grf > --- > Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml > index 3be3cfd52f7b..4564ff0bfd7a 100644 > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml > @@ -14,6 +14,9 @@ properties: > oneOf: > - items: > - enum: > + - rockchip,rk3568-pcie3-phy-grf > + - rockchip,rk3588-pcie3-phy-grf > + - rockchip,rk3588-pcie3-pipe-grf Order is now messed up. > - rockchip,rk3288-sgrf > - rockchip,rk3566-pipe-grf > - rockchip,rk3568-usb2phy-grf Best regards, Krzysztof
