Hi Shimoda-san,
On Wed, Apr 20, 2022 at 10:31 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> Add UFS node for R-Car S4-8 (r8a779f0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> @@ -40,6 +40,13 @@ extalr_clk: extalr {
> clock-frequency = <0>;
> };
>
> + ufs30_clk: ufs30-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
This matches what we typically do for the PCIe reference clock,
but relies on the currently-missing clock generator initialization
in the boot loader stack.
> +
> pmu_a55 {
> compatible = "arm,cortex-a55-pmu";
> interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> @@ -258,6 +265,18 @@ i2c5: i2c@e66e0000 {
> status = "disabled";
> };
>
> + ufs: ufs@e6860000 {
> + compatible = "renesas,r8a779f0-ufs";
> + reg = <0 0xe6860000 0 0x100>;
> + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
The R-Car S4-8 interrupt mapping spreadsheet lists two interrupts.
> + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
> + clock-names = "fck", "ref_clk";
> + freq-table-hz = <200000000 200000000>, <38400000 38400000>;
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 1514>;
> + status = "disabled";
> + };
> +
> scif3: serial@e6c50000 {
> compatible = "renesas,scif-r8a779f0",
> "renesas,rcar-gen4-scif", "renesas,scif";
The rest LGTM, so with the above resolved:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
