I have replied with my Tested-by to the patch at [2], which has landed
in the linux-next as the commit 8ae0117418f3 ("PCI: qcom:
Add support for handling MSIs from 8 endpoints"). However lately I
noticed that during the tests I still had 'pcie_pme=nomsi', so the
device was not forced to use higher MSI vectors.
After removing this option I noticed that hight MSI vectors are not
delivered on tested platforms. After additional research I stumbled upon
a patch in msm-4.14 ([1]), which describes that each group of MSI
vectors is mapped to the separate interrupt. Implement corresponding
mapping.
Patchseries dependecies: [2] (landed in pci-next) and [3] (for the
schema change).
Changes since v2:
- Fix and rephrase commit message for patch 2.
Changes since v1:
- Split a huge patch into three patches as suggested by Bjorn Helgaas
- snps,dw-pcie removal is now part of [3]
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22
[2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@xxxxxxxxxx/
[3] https://lore.kernel.org/linux-arm-msm/20220422211002.2012070-1-dmitry.baryshkov@xxxxxxxxxx/
Dmitry Baryshkov (5):
PCI: dwc: Convert msi_irq to the array
PCI: dwc: Teach dwc core to parse additional MSI interrupts
PCI: qcom: Handle MSI IRQs properly
dt-bindings: pci/qcom,pcie: support additional MSI interrupts
arm64: dts: qcom: sm8250: provide additional MSI interrupts
.../devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++-
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-exynos.c | 2 +-
.../pci/controller/dwc/pcie-designware-host.c | 53 ++++++++++++++-----
drivers/pci/controller/dwc/pcie-designware.h | 3 +-
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +-
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
10 files changed, 69 insertions(+), 21 deletions(-)
--
2.35.1
