Il 22/04/22 08:01, Rex-BC Chen ha scritto:
There are two versions for clock reset register control of MediaTek SoCs. The old hardware is one bit per reset control, and does not have separate registers for bit set, clear and read-back operations. This matches the scheme supported by the simple reset driver. However, because we need to use our data structure "struct mtk_reset", we can not use the operation of simple reset driver. We keep the original functions and name this version as "MTK_RST_SIMPLE". In this patch: - Add a version enum to separate different MediaTek reset hardware. - Merge the reset register function of simple and set_clr into one function "mtk_register_reset_controller". - Rename input variable "num_regs" to "rst_set_nr" to avoid confusion. This variable is used to define the number of reset set. - Rename "regofs" to "reg_ofs". - Adjust delaration type for mtk_register_reset_controller(). Signed-off-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
