On Thu, Apr 21, 2022 at 9:55 AM Sander Vanheule <sander@xxxxxxxxxxxxx> wrote: > The kernel for RTL930x SoC is built with CONFIG_CPU_BIG_ENDIAN=y, just like the > older SoCs that were previously supported. The SoC's IRQ controller is also the > same across RTL930x/RTL839x/RTL838x, even though 32-bit registers are used > there. > > On RTL838x/RTL839x the GPIO IRQ control registers have byte layout: > [H1] [L1] [H2] [L2] > [H3] [L3] [H4] [L4] > > On RTL930x, the GPIO IRQ control registers are: > [H2] [L2] [H1] [L1] > [H4] [L4] [H3] [L3] > which is the reverse of: > [L1] [H1] [L2] [H2] > [L3] [H3] [L4] [H4] > > > Same for the GPIO registers: > On RTL83xx: [P1] [P2] [P3] [P4] (four 8b ports) > On RTL930x: [P4] [P3] [P2] [P1] (one BE32 port) > > It looks like the RTL930x could use a little-endian interpretation of the 32b > registers, followed by a little-endian interpretation of the contained port > values. That would mean two reorderings for every 16b read or write operation, > and manual manipulation of the register values. Although I have to say that the > current offset calculation is not too pretty either. I'm happy. It's not very invasive and the bulk of the problem is addressed by simply using the GPIO MMIO library, so: Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx> If someone knows a more elegant way, they can send a patch, this works so we should merge it. Yours, Linus Walleij
