On Thu, Mar 03, 2022 at 05:35:43PM -0500, Sean Anderson wrote: > This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly > found on Xilinx FPGAs. At the moment clock control is very basic: we > just enable the clock during probe and pin the frequency. In the future, > someone could add support for disabling the clock when not in use. > > Some common code has been specially demarcated. While currently only > used by the PWM driver, it is anticipated that it may be split off in > the future to be used by the timer driver as well. > > This driver was written with reference to Xilinx DS764 for v1.03.a [1]. > > [1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf > > Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> > Acked-by: Michal Simek <michal.simek@xxxxxxxxxx> > --- > > Changes in v14: > - 1GHz -> 1 GHz > - Clarify that we will give a very wrong estimate for rate >= 1 GHz > - Remove duplicate blank line > - Remove forward declaration of xilinx_timer_common_init (which no > longer exists). > > Changes in v13: > - Clamp period/duty_cycle by assuming rate is at most U32_MAX > - Expand comment in xilinx_timer_get_period > - Note that the 100% duty cycle calculations may be wrong for very high > clock rates > > Changes in v12: > - Add a comment to the timer driver about #pwm-cells > - Combine/expand comments on rounding in xilinx_pwm_apply > > Changes in v11: > - Add comment about why we test for #pwm-cells > - Clarify comment on generate out signal > - Rename pwm variables to xilinx_pwm > - Round like Uwe wants... > - s/xilinx_timer/xilinx_pwm/ for non-common functions > > Changes in v10: > - Fix compilation error in timer driver > > Changes in v9: > - Refactor "if { return } else if { }" to "if { return } if { }" > - Remove drivers/clocksource/timer-xilinx-common.c from MAINTAINERS > - Remove xilinx_timer_common_init and integrate it into xilinx_timer_probe > > Changes in v8: > - Drop new timer driver; it has been deferred for future series > > Changes in v7: > - Add dependency on OF_ADDRESS > - Fix period_cycles calculation > - Fix typo in limitations > > Changes in v6: > - Capitalize error messages > - Don't disable regmap locking to allow inspection of registers via > debugfs > - Prevent overflow when calculating period_cycles > - Remove enabled variable from xilinx_pwm_apply > - Swap order of period_cycle range comparisons > > Changes in v5: > - Allow non-zero #pwm-cells > - Correctly set duty_cycle in get_state when TLR0=TLR1 > - Elaborate on limitation section > - Perform some additional checks/rounding in apply_state > - Remove xlnx,axi-timer-2.0 compatible string > - Rework duty-cycle and period calculations with feedback from Uwe > - Switch to regmap to abstract endianness issues > - Use more verbose error messages > > Changes in v4: > - Don't use volatile in read/write replacements. Some arches have it and > some don't. > - Put common timer properties into their own struct to better reuse > code. > - Remove references to properties which are not good enough for Linux. > > Changes in v3: > - Add clockevent and clocksource support > - Remove old microblaze driver > - Rewrite probe to only use a device_node, since timers may need to be > initialized before we have proper devices. This does bloat the code a bit > since we can no longer rely on helpers such as dev_err_probe. We also > cannot rely on device resources being free'd on failure, so we must free > them manually. > - We now access registers through xilinx_timer_(read|write). This allows us > to deal with endianness issues, as originally seen in the microblaze > driver. CAVEAT EMPTOR: I have not tested this on big-endian! > > Changes in v2: > - Add comment describing device > - Add comment explaining why we depend on !MICROBLAZE > - Add dependencies on COMMON_CLK and HAS_IOMEM > - Cast dividends to u64 to avoid overflow > - Check for over- and underflow when calculating TLR > - Check range of xlnx,count-width > - Don't compile this module by default for arm64 > - Don't set pwmchip.base to -1 > - Ensure the clock is always running when the pwm is registered > - Remove debugfs file :l > - Rename TCSR_(SET|CLEAR) to TCSR_RUN_(SET|CLEAR) > - Report errors with dev_error_probe > - Set xilinx_pwm_ops.owner > - Use NSEC_TO_SEC instead of defining our own > - Use TCSR_RUN_MASK to check if the PWM is enabled, as suggested by Uwe > > MAINTAINERS | 6 + > arch/microblaze/kernel/timer.c | 4 + > drivers/pwm/Kconfig | 14 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-xilinx.c | 321 +++++++++++++++++++++++++++++ > include/clocksource/timer-xilinx.h | 73 +++++++ > 6 files changed, 419 insertions(+) > create mode 100644 drivers/pwm/pwm-xilinx.c > create mode 100644 include/clocksource/timer-xilinx.h Applied with Uwe's s/>= 1 GHz/> 1 GHz/ ask applied. I've also changed the MODULE_LICENSE string to just "GPL" since that's what checkpatch requested. Thanks, Thierry
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