Re: [PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

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On 13/04/2022 16:19, Dmitry Baryshkov wrote:
On 09/03/2022 22:01, Ansuel Smith wrote:
The current value for pci IO is problematic for ath10k wifi card
commonly connected to ipq8064 SoC.
The current value is probably a typo and is actually uncommon to find
1MB IO space even on a x86 arch.

I checked other Qualcomm platforms (including downstream apq8084.dtsi). All of them list 1MB region as IO space.

Interesting enough I couldn't get PCI to work on my IFC6410 (apq8064). It has an ethernet adapter AR8151 sitting on the PCIe bus. The driver probes, transmits packets successfully, but receives only garbage. I'm not sure if it is the hardware or a software problem. Same adapter works fine on db820c.

I noticed that it looks like the packet is shifted by two bytes. Maybe it's some weird maths somewhere. Maybe it's the lack of iommu on apq8064. Anyway, it seems to be unrelated to the issue being discussed.


Also with recent changes to the pci
driver, pci1 and pci2 now fails to function as any connected device
fails any reg read/write. Reduce this to 64K as it should be more than
enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
hardcoded for the ARM arch.

Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
Tested-by: Jonathan McDowell <noodles@xxxxxxxx>
---
  arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e247bf51df01..36bdfc8db3f0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
              #address-cells = <3>;
              #size-cells = <2>;
-            ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */ +            ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */                     0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
              interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
              #address-cells = <3>;
              #size-cells = <2>;
-            ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */ +            ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */                     0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
              interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
              #address-cells = <3>;
              #size-cells = <2>;
-            ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */ +            ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */                     0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
              interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;




--
With best wishes
Dmitry



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