On 09/04/2022 12:16, Marc Zyngier wrote: > A common mistake when writing a device tree for a platform that is using > GICv3 with ancient CPUs is to overlook the MMIO frames that implement > the GICv2 compatibility feature, because this feature is implemented by > the CPUs and not by the GIC itself. > > The compatibility feature itself is optional (all the modern > implementations have dropped it), but is present in all the ARM Ltd > implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73), > and many others from various implementers. > > Make it explicit that GICC, GICH and GICV are required for these CPUs. > Also take this opportunity to update my email address, as people keep > sending them to the wrong place... > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx> > --- > .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
