On 08/04/2022 06:58, Rex-BC Chen wrote: > From: Jia-Wei Chang <jia-wei.chang@xxxxxxxxxxxx> > > MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module > for scaling clock frequency and adjust voltage. > The phandle could be linked between CPU and MediaTek CCI for some > MediaTek SoCs, like MT8183 and MT8186. > Therefore, we add this property in cpufreq-mediatek.txt. > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@xxxxxxxxxxxx> > Signed-off-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx> > --- > .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > index b8233ec91d3d..d1b3d430c25c 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > @@ -20,6 +20,10 @@ Optional properties: > Vsram to fit SoC specific needs. When absent, the voltage scaling > flow is handled by hardware, hence no software "voltage tracking" is > needed. > +- cci: MediaTek Cache Coherent Interconnect uses software devfreq module for scaling > + clock frequency and adjust voltage. You need to describe the type. I am a bit confused whether this is a cci (so cci-control-port property?) or an interconnect (so interconnect property)... It does not look like a generic property, so you need vendor prefix. > + For details, please refer to > + Documentation/devicetree/bindings/devfreq/mtk-cci.yaml Such file does not exist. Best regards, Krzysztof
