Convert the device tree bindings for the AXS10x reset controller to YAML
schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@xxxxxxxxxxxx>
---
.../bindings/reset/snps,axs10x-reset.txt | 33 -------------
.../bindings/reset/snps,axs10x-reset.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
create mode 100644 Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
deleted file mode 100644
index 32d8435a41df..000000000000
--- a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Binding for the AXS10x reset controller
-
-This binding describes the ARC AXS10x boards custom IP-block which allows
-to control reset signals of selected peripherals. For example DW GMAC, etc...
-This block is controlled via memory-mapped register (AKA CREG) which
-represents up-to 32 reset lines.
-
-As of today only the following lines are used:
- - DW GMAC - line 5
-
-This binding uses the common reset binding[1].
-
-[1] Documentation/devicetree/bindings/reset/reset.txt
-
-Required properties:
-- compatible: should be "snps,axs10x-reset".
-- reg: should always contain pair address - length: for creg reset
- bits register.
-- #reset-cells: from common reset binding; Should always be set to 1.
-
-Example:
- reset: reset-controller@11220 {
- compatible = "snps,axs10x-reset";
- #reset-cells = <1>;
- reg = <0x11220 0x4>;
- };
-
-Specifying reset lines connected to IP modules:
- ethernet@.... {
- ....
- resets = <&reset 5>;
- ....
- };
diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml
new file mode 100644
index 000000000000..a75db3d405af
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AXS10x reset controller
+
+maintainers:
+ - Eugeniy Paltsev <Eugeniy.Paltsev@xxxxxxxxxxxx>
+
+description: |
+ This binding describes the ARC AXS10x boards custom IP-block which allows
+ to control reset signals of selected peripherals. For example DW GMAC, etc...
+ This block is controlled via memory-mapped register (AKA CREG) which
+ represents up-to 32 reset lines.
+ As of today only the following lines are used:
+ - DW GMAC - line 5
+
+properties:
+ compatible:
+ const: snps,axs10x-reset
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@11220 {
+ compatible = "snps,axs10x-reset";
+ #reset-cells = <1>;
+ reg = <0x11220 0x4>;
+ };
+
+ // Specifying reset lines connected to IP modules:
+ ethernet {
+ resets = <&reset 5>;
+ };
--
2.30.2
