On 4/7/22 13:54, Kavyasree Kotagiri wrote: > LAN966x SoC supports 3 QSPI controllers. Each of them support > data and clock frequency upto 100Mhz DDR and QUAD protocol. How is this IP different than microchip,sama7g5-qspi? Does this speed limitation come from the IP itself or from the board that you're using? Neither of these instances support octal mode? Cheers, ta > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > index 1d493add4053..100d6e7f2748 100644 > --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > @@ -19,6 +19,7 @@ properties: > - microchip,sam9x60-qspi > - microchip,sama7g5-qspi > - microchip,sama7g5-ospi > + - microchip,lan966x-qspi > > reg: > items:
