On Thu, 2022-03-10 at 14:44 -0600, Rob Herring wrote: > On Mon, Mar 07, 2022 at 08:21:49PM +0800, Tim Chang wrote: > > 1. add cci property. > > 2. add example of MT8186. > > > > Signed-off-by: Jia-Wei Chang < > > jia-wei.chang@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> > > --- > > .../bindings/cpufreq/cpufreq-mediatek.yaml | 41 > > +++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq- > > mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq- > > mediatek.yaml > > index 584946eb3790..d3ce17fd8fcf 100644 > > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq- > > mediatek.yaml > > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq- > > mediatek.yaml > > @@ -48,6 +48,10 @@ properties: > > When absent, the voltage scaling flow is handled by > > hardware, hence no > > software "voltage tracking" is needed. > > > > + cci: > > + description: > > + Phandle of the cci to be linked with the phandle of CPU if > > present. > > We already have a binding for this. See cci-control-port. Hi Rob, Pardon me for my late reply. It seems that "cci-control-port" is hardware IP from ARM. But mediatek-cpufreq uses MTK internal CCI hardware IP. I think I should keep this change here. Thanks. > > > + > > "#cooling-cells": > > description: > > For details, please refer to
