On Tue, Apr 05, 2022 at 05:19:28PM +0800, Andy Chiu wrote:
> Document the new pcs-handle attribute to support connecting to an
> external PHY. For Xilinx's AXI Ethernet, this is used when the core
> operates in SGMII or 1000Base-X modes and links through the internal
> PCS/PMA PHY.
>
> Signed-off-by: Andy Chiu <andy.chiu@xxxxxxxxxx>
> Reviewed-by: Greentime Hu <greentime.hu@xxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
Andrew
