On Tue, 29 Mar 2022 10:49:20 +0800, Andy Chiu wrote: > Document the new pcs-handle attribute to support connecting to an > external PHY. For Xilinx's AXI Ethernet, this is used when the core > operates in SGMII or 1000Base-X modes and links through the internal > PCS/PMA PHY. > > Signed-off-by: Andy Chiu <andy.chiu@xxxxxxxxxx> > Reviewed-by: Greentime Hu <greentime.hu@xxxxxxxxxx> > --- > .../devicetree/bindings/net/ethernet-controller.yaml | 6 ++++++ > Documentation/devicetree/bindings/net/xilinx_axienet.txt | 8 +++++++- > 2 files changed, 13 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
