On Wed, Mar 30, 2022 at 04:48:47PM +0800, Irui Wang wrote: > Dear Rob, > > A sample encoder hardware block diagram attached. > On Tue, 2022-03-29 at 08:09 -0500, Rob Herring wrote: > > On Tue, Mar 29, 2022 at 09:26:37AM +0800, Irui Wang wrote: > > > Dear Rob, > > > > > > Many thanks for your attention. > > > > > > On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote: > > > > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > > > > > Dear Rob, > > > > > > > > > > Thanks for your review and comments. > > > > > > > > > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > > > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > > > > > Adds encoder cores dt-bindings for mt8195. > > > > [...] > > > > > > > > > + mediatek,core-id: > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > > + description: | > > > > > > > + Current encoder core id. > > > > > > > > > > > > What is this for and what does its value correspond to in the > > > > > > h/w. > > > > > > We > > > > > > generally don't do made up indices in DT. > > > > > > > > > > It's for encoder core id, core@1a020000 must be core-0, > > > > > core@1b020000 > > > > > must be core-1, we add this property in each child node, so we > > > > > can > > > > > get core-id in drivers. If it can't ref "uint32" types yaml, > > > > > would > > > > > you mind giving some more suggestions ? > > > > > > > > I still don't understand why it is needed. What is 'core-0'? > > > > > > > > Is there some functional difference between the cores? If so, > > > > describe > > > > that difference. > > > > > > > > Rob > > > > > > They are two different pieces of hardware, it's our encoder > > > hardware > > > design. There are two encoder hardware cores inside MT8195, named > > > core0 > > > and core1(we can rename it, but core id should be declared), > > > for core0, its module base address is 0x1A02_0000, uses IOMMU > > > "vdo0_iommu" and power domain "POWER_DOMAIN_VENC", > > > for core1, its module base address is 0x1B02_0000, uses IOMMU > > > "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1". > > > So the two encoder cores have their own base, IRQ, clock, power, > > > etc. > > > Each core can encode independently, moreover, they can work > > > together > > > for higher performance. > > > We will describe more details in YAML about it if it's OK for you. > > > > All the resources you list are in the child nodes, so you don't need > > 0 > > and 1 numbering for those. > > > > Looking at the driver patches, the only thing I see distinguishing > > core numbers is this: > > > > "frame#0 uses core#0, frame#1 uses core#1, frame#2 uses core#0..., > > > > Lock the device and enable the clock by used core, for sequence > > header encoding, it always uses core#0." > > > > Is this a requirement in the h/w or just what the driver picked? > > IOW, > > could frame#0 use core#1? > No, it's a requirement in the h/w, driver trigger core start encoding > is in order. > About the encoder hardware block diagram, please check below: > -------------------------------------------------------------- > Input Buffer: 0 1 2 3 4 5 6 > | | | | | | | > v | v | v | v > +-------+ | +-------+ | +-------+ | +-------+ > | core0 | | | core0 | | | core0 | | | core0 | > +-------+ | +-------+ | +-------+ | +-------+ > | | | | | | | > | v | v | v | > | +-------+ | +-------+ | +-------+ | > | | core1 | | | core1 | | | core1 | | > | +-------+ | +-------+ | +-------+ | > | | | | | | | > v v v v v v v <parent> > -------------------------------------------------------------- > core || index <child> > \/ > +-----------------------------------------------+ > | core0/core1 | > | enable/disable power/clk/irq | > +-----------------------------------------------+ > -------------------------------------------------------------- > As above , there are parent and child devices, child mean each venc > core, the child device controls the information of each core > independent which inlcude power/clk/irq. > When start encoding, input buffer 0 will be encoded by core0, and input > buffer 1 can be encoded by core1 even if buffer 0 has not been encoded > done yet, after buffer 0 encoded done, buffer 2 will be encoded by > core0, and buffer 1 encoded done by core1. These two encoder cores will > encode each input in this overlapping manner. > > We need manage each child device in parent device by core-id property. > And we also need record current encoding input buffer, encode done > output buffers and which one core is in used through core-id, because > the two cores are encoding at the same time under one parent driver. Okay, please summarize the h/w requirement in the property description. You might put the above diagram in the top description too. Rob
