Hi CK, Thanks for the reviews. On Fri, 2022-03-18 at 15:21 +0800, CK Hu wrote: > Hi, Jason: > > On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote: > > Add mtk-mutex support for mt8195 vdosys0. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@xxxxxxxxxxxx> > > Acked-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@xxxxxxxxxxxxx> > > --- > > drivers/soc/mediatek/mtk-mutex.c | 103 > > ++++++++++++++++++++++++++++++- > > 1 file changed, 100 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > > b/drivers/soc/mediatek/mtk-mutex.c > > index aaf8fc1abb43..1c7ffcdadcea 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -17,6 +17,9 @@ > > #define MT8183_MUTEX0_MOD0 0x30 > > #define MT8183_MUTEX0_SOF0 0x2c > > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30 > > +#define MT8195_DISP_MUTEX0_SOF 0x2c > > + > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * > > (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * > > (n)) > > @@ -96,6 +99,36 @@ > > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > > #define MT8173_MUTEX_MOD_DISP_OD 25 > > [snip] > > > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 > > > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 > > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 > > > > > > Useless, remove. > > > > > > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 > > > > > > Ditto. > > > > > > Regards, > > > CK > > > > Although these definitions are not used, they represent the > > functionality provided by this register. > > > > I think we can show that we have these capabilities by defining > them. > > > > Can we keep these definitions? > > OK, but add some information that we could know how to use it. What's > these DL_RELAY and when should we add these to mutex? > > Regards, > CK DL_RELAY is used for the cross mmsys mux settings. We won't use these setting currently, so I think I just remove these useless define. Thanks. Regards, Jason-JH.Lin [snip] -- Jason-JH Lin <jason-jh.lin@xxxxxxxxxxxx>