On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add the device tree node for the SGPIO IP block reused from the
> SparX-5. Keep the node disabled by default.
>
> Signed-off-by: Michael Walle <michael@xxxxxxxx>
Reviewed-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 5e9cbc8cdcbc..39dfdb8e29ed 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
> #interrupt-cells = <2>;
> };
>
> + sgpio: gpio@e2004190 {
> + compatible = "microchip,sparx5-sgpio";
> + reg = <0xe2004190 0x118>;
> + clocks = <&sys_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgpio_in: gpio@0 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + sgpio_out: gpio@1 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + };
> + };
> +
> gic: interrupt-controller@e8c11000 {
> compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> --
> 2.30.2
>
