On Fri, Mar 25, 2022 at 06:29:05PM +0100, Krzysztof Kozlowski wrote: > On 25/03/2022 14:36, Rui Miguel Silva wrote: > > Add bindings to describe the FPGA in a prototyping board > > (MPS3) implementation and the Fixed Virtual Platform > > implementation of the ARM Corstone1000 platform. > > > > Signed-off-by: Rui Miguel Silva <rui.silva@xxxxxxxxxx> > > --- > > .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > new file mode 100644 > > index 000000000000..a77f88223801 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > @@ -0,0 +1,45 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ARM Corstone1000 Device Tree Bindings > > + > > +maintainers: > > + - Vishnu Banavath <vishnu.banavath@xxxxxxx> > > + - Rui Miguel Silva <rui.silva@xxxxxxxxxx> > > + > > +description: |+ > > + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that > > + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M > > + processors. > > + > > + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion > > + systems for M-Class (or other) processors for adding sensors, connectivity, > > + video, audio and machine learning at the edge System and security IPs to build > > + a secure SoC for a range of rich IoT applications, for example gateways, smart > > + cameras and embedded systems. > > + > > + Integrated Secure Enclave providing hardware Root of Trust and supporting > > + seamless integration of the optional CryptoCell™-312 cryptographic > > + accelerator. > > + > > +properties: > > + $nodename: > > + const: '/' > > + compatible: > > + oneOf: > > + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA > > + implementation of the Corstone1000 in the MPS3 prototyping board. See > > + ARM document DAI0550. > > + items: > > + - const: arm,corstone1000-mps3 > > If I understood correctly your description and DAI0550, the MPS3 board > is a board with Corstone 100, so you miss here compatible for the chip > (e.g. arm,corstone1000). > > I guess similar pattern for the FVP, so both should be combined within > an enum (skipping all this description). Corstone1000 is a collection of IP that would be the basis for an SoC. These 2 are FVP and FPGA implementations of corstone1000 with additional IP to make them usable (e.g. USB and ethernet). Each one as a whole is a one off AIUI. So I don't think they really fit into our board plus SoC compatible patten and are fine as-is. Rob
