This series patches include newly PCIe support for Axis ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications. PCIe controller driver and phy driver have been newly added. There is also a new MAINTAINER in the addition of phy driver. PCIe controller is designed based on Design-Ware PCIe controller IP and PCIe phy is desinged based on SAMSUNG PHY IP. It also includes modifications to the Design-Ware controller driver to run the 64bit-based ARTPEC-8 PCIe controller driver. It consists of 6 patches in total. This series has been tested on AXIS SW bring-up board with ARTPEC-8 chipset. wangseok.lee (5): dt-bindings: pci: Add ARTPEC-8 PCIe controller dt-bindings: phy: Add ARTPEC-8 PCIe phy PCI: axis: Add ARTPEC-8 PCIe controller driver phy: Add ARTPEC-8 PCIe PHY driver MAINTAINERS: Add maintainer for Axis ARTPEC-8 PCIe PHY driver .../bindings/pci/axis,artpec8-pcie-ep.yaml | 110 +++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 117 +++ .../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++ MAINTAINERS | 2 + drivers/pci/controller/dwc/Kconfig | 31 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec8.c | 912 +++++++++++++++++++++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/artpec/Kconfig | 9 + drivers/phy/artpec/Makefile | 2 + drivers/phy/artpec/phy-artpec8-pcie.c | 879 ++++++++++++++++++++ 12 files changed, 2132 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml create mode 100644 drivers/pci/controller/dwc/pcie-artpec8.c create mode 100644 drivers/phy/artpec/Kconfig create mode 100644 drivers/phy/artpec/Makefile create mode 100644 drivers/phy/artpec/phy-artpec8-pcie.c -- 2.9.5
