On Fri, Mar 25, 2022 at 01:36:55PM +0000, Rui Miguel Silva wrote: > Corstone1000 is a platform from arm, which includes pre > verified Corstone SSE710 sub-system that combines Cortex-A and > Cortex-M processors [0]. > > These device trees contains the necessary bits to support the > Corstone 1000 FVP (Fixed Virtual Platform) [1] and the > FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host > side of this platform. [2] > > 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 > 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps > 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf > > Signed-off-by: Rui Miguel Silva <rui.silva@xxxxxxxxxx> > --- > arch/arm64/boot/dts/arm/Makefile | 1 + > arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ > arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ > arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ > 4 files changed, 221 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi Please run 'make dtbs_check' on these and fix any errors. > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile > index 4382b73baef5..d908e96d7ddc 100644 > --- a/arch/arm64/boot/dts/arm/Makefile > +++ b/arch/arm64/boot/dts/arm/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb > +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb > diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > new file mode 100644 > index 000000000000..8f6ce94b4d5a > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: BSD-3-Clause While nothing is shared, the existing Arm, Ltd dts files here are GPL2 only or GPL/BSD. The preference for dts files is dual GPL2 and BSD/MIT > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; > + compatible = "arm,corstone1000-fvp"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan91c111"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 116 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > new file mode 100644 > index 000000000000..922253f0af07 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FPGA MPS3 board"; > + compatible = "arm,corstone1000-mps3"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan9220", "smsc,lan9115"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > + usb: usb@40200000 { > + compatible = "nxp,usb-isp1763"; > + reg = <0x40200000 0x100000>; > + interrupts-parent = <&gic>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + bus-width = <16>; > + dr_mode = "host"; > + }; > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi > new file mode 100644 > index 000000000000..eb423af84e9f > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi > @@ -0,0 +1,151 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + chosen { > + stdout-path = "/uart@1a510000:115200n8"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; This compatible is only valid for models. The FPGA should have something else. > + reg = <0>; > + next-level-cache = <&L2_0>; > + }; > + }; > + > + memory@88200000 { > + device_type = "memory"; > + reg = <0x88200000 0x77e00000>; > + }; > + > + gic: interrupt-controller@1c000000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x1c010000 0x1000>, > + <0x1c02f000 0x2000>, > + <0x1c04f000 0x1000>, > + <0x1c06f000 0x2000>; > + interrupts = <1 9 0xf08>; > + }; > + > + L2_0: l2-cache0 { > + compatible = "cache"; > + }; > + > + refclk100mhz: refclk100mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "apb_pclk"; > + }; > + > + smbclk: refclk24mhzx2 { > + /* Reference 24MHz clock x 2 */ > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <48000000>; > + clock-output-names = "smclk"; > + }; > + > + uartclk: uartclk { > + /* UART clock - 50MHz */ > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "uartclk"; > + }; > + > + serial0: uart@1a510000 { Place nodes with an MMIO address under one (or more) simple-bus nodes. You might want that to align with what's in the the SSE710 subsystem and not in it. > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x1a510000 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartclk>, <&refclk100mhz>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + refclk: refclk@1a220000 { refclk? > + compatible = "arm,armv7-timer-mem"; > + reg = <0x1a220000 0x1000>; 1 space ^^ > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + frame@1a230000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; > + reg = <0x1a230000 0x1000>; > + }; > + }; > + > + mbox_es0mhu0: mhu@1b000000 { mailbox@... > + compatible = "arm,mhuv2","arm,primecell"; space ^ > + reg = <0x1b000000 0x1000>, > + <0x1b010000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-es0-mhu0"; It's 'mbox-names', but that's a consumer, not provider property. You should see a warning for this. > + }; > + > + mbox_es0mhu1: mhu@1b020000 { > + compatible = "arm,mhuv2","arm,primecell"; > + reg = <0x1b020000 0x1000>, > + <0x1b030000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-es0-mhu1"; > + }; > + > + mbox_semhu1: mhu@1b820000 { > + compatible = "arm,mhuv2","arm,primecell"; > + reg = <0x1b820000 0x1000>, > + <0x1b830000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-se-mhu1"; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > +}; > -- > 2.35.1 > >
