On Sun, 13 Mar 2022 16:46:39 +0100, Michael Walle wrote: > On the LAN966x SoC the GPIO controller will be resetted together with > the SGPIO and the switch core. Add a phandle to register the shared > reset line. > > Signed-off-by: Michael Walle <michael@xxxxxxxx> > --- > .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
