On Fri, Mar 18, 2022 at 10:45:21PM +0800, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
> };
> };
>
> + pcie: pcie@11230000 {
> + compatible = "mediatek,mt8192-pcie";
> + device_type = "pci";
> + reg = <0 0x11230000 0 0x2000>;
> + reg-names = "pcie-mac";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> + <&infracfg CLK_INFRA_PCIE_TL_96M>,
> + <&infracfg CLK_INFRA_PCIE_TL_32K>,
> + <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> + <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> + "obff_ck0", "axi_ck0", "pipe_ck0";
> + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> + resets = <&infracfg_rst 2>,
> + <&infracfg_rst 3>;
> + reset-names = "phy", "mac";
> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> + <0 0 0 2 &pcie_intc0 1>,
> + <0 0 0 3 &pcie_intc0 2>,
> + <0 0 0 4 &pcie_intc0 3>;
> +
> + pcie_intc0: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> --
> 2.18.0
>
>
