Re: [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186

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On 3/20/2022 6:12 PM, Krzysztof Kozlowski wrote:
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On 16/03/2022 10:25, Ashish Mhetre wrote:
 From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels.
Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers.
So update the reg maxItems to 18 in tegra186 devicetree documentation.

Signed-off-by: Ashish Mhetre <amhetre@xxxxxxxxxx>
---
  .../nvidia,tegra186-mc.yaml                   | 20 +++++++++++++------
  1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 13c4c82fd0d3..3c4e231dc1de 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,8 +34,8 @@ properties:
            - nvidia,tegra234-mc

    reg:
-    minItems: 1
-    maxItems: 3
+    minItems: 6
+    maxItems: 18

Still ABI break and now the in-kernel DTS will report dt check errors.

The dt check error is because I mistakenly updated example in EMC node
instead of MC. I'll fix it in next version.

I think you ignored the comments you got about breaking ABI.

No, I took care of the ABI break in v5. I have updated details about
how we took care of it in first patch.

Best regards,
Krzysztof



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