Add AMP enable node and pinmux for primary and secondary I2S
for SC7280 based platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 34 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 21 +++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 41 ++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index dc17f20..de646d9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -530,6 +530,26 @@ ap_ec_spi: &spi10 {
drive-strength = <2>;
};
+&pri_mi2s_data0 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_data1 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_mclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_sclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_ws {
+ drive-strength = <6>;
+};
+
&qspi_cs0 {
bias-disable;
drive-strength = <8>;
@@ -610,6 +630,20 @@ ap_ec_spi: &spi10 {
drive-strength = <10>;
};
+&sec_mi2s_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_ws {
+ drive-strength = <6>;
+};
+
/* PINCTRL - board-specific pinctrl */
&pm7325_gpios {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 688fa95..4a7b18a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -462,7 +462,28 @@
drive-strength = <10>;
};
+&sec_mi2s_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_ws {
+ drive-strength = <6>;
+};
+
&tlmm {
+ amp_en: amp-en {
+ pins = "gpio63";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
bt_en: bt-en {
pins = "gpio85";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f0b64be..8d8cec5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3527,6 +3527,31 @@
function = "pcie1_clkreqn";
};
+ pri_mi2s_data0: pri-mi2s-data0 {
+ pins = "gpio98";
+ function = "mi2s0_data0";
+ };
+
+ pri_mi2s_data1: pri-mi2s-data1 {
+ pins = "gpio99";
+ function = "mi2s0_data1";
+ };
+
+ pri_mi2s_mclk: pri-mi2s-mclk {
+ pins = "gpio96";
+ function = "pri_mi2s";
+ };
+
+ pri_mi2s_sclk: pri-mi2s-sclk {
+ pins = "gpio97";
+ function = "mi2s0_sck";
+ };
+
+ pri_mi2s_ws: pri-mi2s-ws {
+ pins = "gpio100";
+ function = "mi2s0_ws";
+ };
+
qspi_clk: qspi-clk {
pins = "gpio14";
function = "qspi_clk";
@@ -4261,6 +4286,22 @@
drive-strength = <2>;
bias-bus-hold;
};
+
+ sec_mi2s_data0: sec-mi2s-data0 {
+ pins = "gpio107";
+ function = "mi2s1_data0";
+ };
+
+ sec_mi2s_sclk: sec-mi2s-sclk {
+ pins = "gpio106";
+ function = "mi2s1_sck";
+ };
+
+ sec_mi2s_ws: sec-mi2s-ws {
+ pins = "gpio108";
+ function = "mi2s1_ws";
+ };
+
};
imem@146a5000 {
--
2.7.4
