On Tue, Jan 25, 2022 at 10:18:21AM -0600, Dinh Nguyen wrote:
> The DWC2 USB controller on the Agilex platform does not support clock
> gating, so use the chip specific "intel,socfpga-agilex-hsotg"
> compatible.
>
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index 0dd2d2ee765a..f4270cf18996 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -502,7 +502,7 @@ uart1: serial@ffc02100 {
> };
>
> usb0: usb@ffb00000 {
> - compatible = "snps,dwc2";
> + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
In the same patchset you sent a bindings change which is contradictory
to this DTS change.
This is wrong here and dtbs_check will complain.
