On 18/03/2022 10:54, Jianjun Wang wrote: > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx> > --- > .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > new file mode 100644 > index 000000000000..868bf976568b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIe PHY > + > +maintainers: > + - Jianjun Wang <jianjun.wang@xxxxxxxxxxxx> > + > +description: | > + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. > + > +properties: > + compatible: > + const: mediatek,mt8195-pcie-phy > + > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - const: sif > + > + "#phy-cells": > + const: 0 > + > + nvmem-cells: > + description: > + Phandles to nvmem cell that contains the efuse data, if unspecified, > + default value is used. maxItems: 7 Best regards, Krzysztof