On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote:
> Add pdc interrupt controller for sm8150.
>
> Cc: Maulik Shah <quic_mkshah@xxxxxxxxxxx>
> Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> Cc: Vinod Koul <vkoul@xxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 6012322a5984..aaeacd379460 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> + reg = <0 0x0b220000 0 0x400>;
> + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> + <125 63 1>;
When I look at the platform documentation I get the impression that this
should be: <0 480 94>, <94 609 32>;
Can you confirm that the last signal is correctly described?
Regards,
Bjorn
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> --
> 2.35.1
>
